1. Technical Field
Various embodiments of the present disclosure relate to methods of fabricating electronic devices including nonvolatile memory devices and, more particularly, to methods of fabricating embedded electronic devices including charge trap flash memory cells.
2. Related Art
In embedded electronic devices provided in system-on-chip (SOC) package form, metal-oxide-semiconductor field effect transistors (MOSFET) may be integrated on a chip or a substrate to constitute various logic devices, interface circuits or nonvolatile memory (NVM) devices. The MOSFETs (MOS transistors) include N-channel MOS transistors (NMOS transistors) and P-channel MOS transistors (PMOS transistors), and the NMOS transistors and the PMOS transistors may constitute a complementary MOS (CMOS) circuit.
The logic devices, the Interface circuits or the nonvolatile memory (NVM) devices may be fabricated using a CMOS process. The CMOS process may include various unit processes. For example, the CMOS process may Include a deposition process for forming a conductive layer, a semiconductor layer or an insulation layer as well as an etch process for patterning the conductive layer, the semiconductor layer or the insulation layer.
The NVM device may be designed to include a plurality of NVM cells, for example, charge trap memory cells having a silicon-oxide-nitride-oxide-silicon (SONOS) type gate structure. The charge trap memory cells having a SONOS-type gate structure are referred to as SONOS memory cells. Each of the SONOS memory cells may have a stacked gate structure including a tunnel Insulation layer, a charge trap layer, an inter-gate insulation layer (a blocking insulation layer), and a control gate layer which are sequentially stacked on a semiconductor substrate. In the event that the charge trap memory cells are integrated on a substrate together with MOS transistors, the blocking insulation layer of the SONOS type gate structure may be formed while a gate insulation layer of the MOS transistors is formed. Thus, the performance of the SONOS memory cells is influenced by the CMOS process.